ST72324J2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72324J2B5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

VIL

Input low level voltage 1)

VIH

Input high level voltage 1)

CMOS ports

Vhys Schmitt trigger voltage hysteresis 2)

IINJ(PIN)3) Injected Current on an I/O pin

ΣIINJ(PIN)3)

Total injected current (sum of all I/O

and control pins)

VDD=5V

0.7xVDD

0.7

IL

Input leakage current

VSS≤VIN≤VDD

IS

Static current consumption

Floating input mode4)

RPU Weak pull-up equivalent resistor 5) VIN=VSS

VDD=5V

50

120

CIO I/O pin capacitance

5

tf(IO)out Output high to low level fall time 1) CL=50pF

25

tr(IO)out Output low to high level rise time 1) Between 10% and 90%

25

tw(IT)in External interrupt pulse time 6)

1

Max

0.3xVDD

±4

± 25

±1

200

250

Unit

V

mA

µA

kΩ

pF

ns

tCPU

Figure 77. Connecting Unused I/O Pins

VDD

ST72XXX

10kΩ

UNUSED I/O PORT

Figure 78. Typical IPU vs. VDD with VIN=VSS

90

80

Ta=1 40°C

Ta=9 5°C

70

Ta=2 5°C

60

Ta=-45 °C

50

40

30

10kΩ

UNUSED I/O PORT

20

ST72XXX

10

0

2 2 .5 3 3 .5 4 4.5 5 5 .5 6

V dd(V )

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-

tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2

on page 114 for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology

characteristics, not tested in production.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 78).

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

135/161

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