CS8427-IS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8427-IS Datasheet PDF : 59 Pages
| |||
CS8427
10. CONTROL PORT REGISTER SUMMARY
Addr
Function
(HEX)
00 Reserved
01 Control 1
02 Control 2
03 Data Flow Control
04 Clock Source Control
05 Serial Input Format
06 Serial Output Format
07 Interrupt 1 Status
08 Interrupt 2 Status
09 Interrupt 1 Mask
0A Interrupt 1 Mode (MSB)
0B Interrupt 1 Mode (LSB)
0C Interrupt 2 Mask
0D Interrupt 2 Mode (MSB)
0E Interrupt 2 Mode (LSB)
0F Receiver CS Data
10 Receiver Errors
11 Receiver Error Mask
12 CS Data Buffer Control
13 U Data Buffer Control
14-1D Q sub-code Data
1E OMCK/RMCK Ratio
1F Reserved
20-37 C or U Data Buffer
7F ID and Version
7
6
5
4
3
2
1
0
0
SWCLK
0
0
0
SIMS
SOMS
TSLIP
0
TSLIPM
TSLIP1
TSLIP0
0
0
0
AUX3
0
0
0
0
0
VSET
HOLD1
TXOFF
RUN
SISF
SOSF
OSLIP
0
OSLIPM
OSLIP1
OSLIP0
0
0
0
AUX2
QCRC
QCRCM
0
0
0
MUTESAO
HOLD0
AESBP
CLK1
SIRES1
SORES1
0
0
0
0
0
0
0
0
AUX1
CCRC
CCRCM
BSEL
0
0
MUTEAES
RMCKF
TXD1
CLK0
SIRES0
SORES0
0
0
0
0
0
0
0
0
AUX0
UNLOCK
UNLOCKM
CBMR
UD
0
0
MMR
TXD0
OUTC
SIJUST
SOJUST
0
DETU
0
0
0
DETUM
DETU1
DETU0
PRO
V
VM
DETCI
UBM1
0
INT1
MMT
SPD1
INC
SIDEL
SODEL
DETC
EFTU
DETCM
DETC1
DETC0
EFTUM
EFTU1
EFTU0
AUDIO
CONF
CONFM
EFTCI
UBM0
0
INT0
MMTCS
SPD0
RXD1
SISPOL
SOSPOL
EFTC
QCH
EFTCM
EFTC1
EFTC0
QCHM
QCH1
QCH0
COPY
BIP
BIPM
CAM
DETUI
0
TCBLD
MMTLR
0
RXD0
SILRPOL
SOLRPOL
RERR
0
RERRM
RERR1
RERR0
0
0
0
ORIG
PAR
PARM
CHS
EFTUI
ORR7 ORR6
ORR5
ORR4
ORR3 ORR2 ORR1
ORR0
ID3
ID2
ID1
ID0
VER3
Table 1. Control Register Map Summary
VER2
VER1
VER0
10.1 Memory Address Pointer (MAP)
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
INCR - Auto Increment Address Control Bit
Default = ‘0’
0 - Disable
1 - Enable
MAP6:MAP0 - Register address
Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test
modes, which can completely alter the normal operation of the CS8427.
DS477F1
27
Share Link: 