CS8427-IS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8427-IS

96 kHz Digital Audio Interface Transceiver

Cirrus Logic 

CS8427

VLRCK

U

Output

VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing.

VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.

If the serial audio output port is in master mode, VLRCK = OLRCK.

If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.

U transitions are aligned within ±1% of VLRCK period to VLRCK edges

Figure 13. AES3 Receiver Timing for U pin output data

Tth

VLRCK

Tsetup

Thold

VCU[0]

VCU[1]

VCU[2]

VCU[3]

VCU[4]

Data [4]

Data [5]

Data [6]

Data [7]

Data [8]

TXP(N)

Z Data [0]

TCBL

Tth

In or Out

VLRCK

U

Input

Y Data [1]

X Data [2]

Y Data [3]

X Data [4]

AES3 Transmitter in Stereo Mode

Tsetup => 7.5% AES3 frame time

Thold = 0

Tth > 3OMCK if TCBL is Input

U[0]

U[2]

SDIN

Input

TXP(N)

Output

Data [4]

Data [5]

Z

Data [0]*

* Assume MMTLR = 0

Data [6]

Data [7]

Y

Data [2]*

Data [8]

X

Data [4]*

TXP(N)

Z

Data [1]*

Y

Data [3]*

X

Data [5]*

Output

* Assume MMTLR = 1

AES3 Transmitter in Mono Mode

Tsetup => 15% AES3 frame time

Thold = 0

Tth > 3OMCK if TCBL is Input

VLRCK is a virtual word clock, which may not exist, is used to illustrate the CUV timing.

VLRCK duty cycle is 50%.

In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.

If the serial audio input port is on slave mode and TCBL is an output, then VLRCK=ILRCK if SILRPOL=0 and

VLRCK= ILRCK if SILRPOL =1.

If the serial audio input port is in master mode and TCBL is an input, then VLRCK=ILRCK if SILRPOL=0 and

VLRCK= ILRCK if SILRPOL =1.

Figure 14. AES3 Transmitter Timing for C, U and V pin input data

22

DS477F1

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