CS8427
mode is used for active low, wired-OR hook-ups
with multiple peripherals connected to the micro-
controller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off using mask register
bits. In addition, each source may be set to rising
edge, falling edge, or level sensitive. Combined
with the option of level sensitive or edge sensitive
modes within the microcontroller, many different
set-ups are possible depending on the needs of
the equipment designer.
CS
CCLK
C D IN
C H IP
ADDRESS
0010000
MAP
DATA
R/W
MSB
LSB
b yte 1 b yte n
C H IP
ADDRESS
0010000 R/W
CDOUT
High Impedance
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 17. Control Port Timing in SPI Mode
SDA
Note 1
Note 2
Note 3
0010 AD2-0 R/W ACK DATA7-0 ACK DATA7-0 ACK
SCL
Start
Stop
Note 1: AD2 is derived from a resistor attached to the EMPH pin,
AD1 and AD0 are determined by the state of the corresponding pins
Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP
Note 3: If operation is a read, the last bit of the read should be a NACK(high)
Figure 18. Control Port Timing in I²C Mode
26
DS477F1