
Figure 43. Peripheral I/O Read Timing
ALE /AS
PSD834F2V
A/D BUS
CSI
RD
ADDRESS
tAVQV (PA)
tSLQV (PA)
tRLQV (PA)
tRLRH (PA)
DATA VALID
tQXRH (PA)
tRHQZ (PA)
tDVQV (PA)
DATA ON PORT A
AI02897
Figure 44. Peripheral I/O Write Timing
ALE /AS
A/D BUS
ADDRESS
WR
DATA OUT
tWLQV (PA)
tWHQZ (PA)
tDVQV (PA)
PORT A
DATA OUT
AI02898
Figure 45. Reset (RESET) Timing
VCC
RESET
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
tOPR
AI02866b
79/89