
PSD834F2V
Figure 36. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
Figure 37. Asynchronous Reset / Preset
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARPW
tARP
Figure 38. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
Figure 39. Asynchronous Clock Mode Timing (product term clock)
tCHA
tCLA
CLOCK
INPUT
REGISTERED
OUTPUT
tSA tHA
tCOA
AI02863
AI02864
AI02860
AI02859
72/89