PSD934F210MIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD934F210MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Figure 29. APD Unit

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

ALE

RESET

CSI

CLKIN

EDGE

DETECT

CLR PD

APD

COUNTER

PD

DISABLE BUS

INTERFACE

EEPROM SELECT

FLASH SELECT

PLD SRAM SELECT

POWER DOWN

(PDN) SELECT

DISABLE

FLASH/EEPROM/SRAM

Automatic Power-down (APD) Unit and Power-

down Mode. The APD Unit, shown in Figure 29,

puts the PSD into Power-down mode by monitor-

ing the activity of Address Strobe (ALE/AS, PD0).

If the APD Unit is enabled, as soon as activity on

Address Strobe (ALE/AS, PD0) stops, a four bit

counter starts counting. If Address Strobe (ALE/

AS, PD0) remains inactive for fifteen clock periods

of CLKIN (PD1), Power-down (PDN) goes High,

and the PSD enters Power-down mode, as dis-

cussed next.

Table 27. Power-down Mode’s Effect on Ports

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

Address Out

Undefined

Data Port

Tri-State

Peripheral I/O

Tri-State

Power-down Mode. By default, if you enable the

APD Unit, Power-down mode is automatically en-

abled. The device enters Power-down mode if Ad-

dress Strobe (ALE/AS, PD0) remains inactive for

fifteen periods of CLKIN (PD1).

The following should be kept in mind when the

PSD is in Power-down mode:

AI02891

s If Address Strobe (ALE/AS, PD0) starts pulsing

again, the PSD returns to normal Operating

mode. The PSD also returns to normal

Operating mode if either PSD Chip Select Input

(CSI, PD2) is Low or the Reset (RESET) input is

High.

s The MCU address/data bus is blocked from all

memory and PLDs.

s Various signals can be blocked (prior to Power-

down mode) from entering the PLDs by setting

the appropriate bits in the PMMR registers. The

blocked signals include MCU control signals

and the common CLKIN (PD1). Note that

blocking CLKIN (PD1) from the PLDs does not

block CLKIN (PD1) from the APD Unit.

s All PSD memories enter Standby mode and are

drawing standby current. However, the PLD and

I/O ports blocks do not go into Standby Mode

because you don’t want to have to wait for the

logic and I/O to “wake-up” before their outputs

can change. See Table 27 for Power-down

mode effects on PSD ports.

s Typical standby current is of the order of

microamperes. These standby current values

assume that there are no transitions on any PLD

input.

Table 28. PSD Timing and Stand-by Current during Power-down Mode

Mode

PLD Propagation Delay

Memory Access

Time

Access Recovery Time to

Normal Access

Typical Stand-by

Current

Power-down Normal tPD (Note 1)

No Access

tLVDV

25 µA (Note 2)

Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.

56/89

Share Link: