PSD934F210MIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD934F210MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Figure 26. Port C Structure

DATA OUT

REG.

DQ

WR

MCELLBC[ 7:0]

DATA OUT

1

SPECIAL FUNCTION

OUTPUT

MUX

PORT C PIN

READ MUX

P

D

DATA IN

B

OUTPUT

SELECT

ENABLE OUT

DIR REG.

DQ

WR

ENABLE PRODUCT TERM (.OE)

CPLD - INPUT

Port C – Functionality and Structure

Port C can be configured to perform one or more

of the following functions (see Figure 26):

s MCU I/O Mode

s CPLD Output – McellBC7-McellBC0 outputs

can be connected to Port B or Port C.

s CPLD Input – via the Input Macrocells (IMC)

s Address In – Additional high address inputs

using the Input Macrocells (IMC).

s In-System Programming (ISP) – JTAG port can

be enabled for programming/erase of the PSD

device. (See the section entitled “Programming

In-Circuit using the JTAG Serial Interface”, on

INPUT

MACROCELL

1

SPECIAL FUNCTION

CONFIGURATION

BIT

AI02888B

page 61, for more information on JTAG

programming.)

s Open Drain – Port C pins can be configured in

Open Drain Mode

s Battery Backup features – PC2 can be

configured for a battery input supply, Voltage

Stand-by (VSTBY).

PC4 can be configured as a Battery-on Indicator

(VBATON), indicating when VCC is less than

VBAT.

Port C does not support Address Out mode, and

therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in

certain MCU bus interfaces.

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