PSD934F210MIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD934F210MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

Figure 27. Port D Structure

DATA OUT

REG.

DQ

WR

ECS[ 2: 0]

READ MUX

P

D

B

DATA OUT

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

PSD834F2V

PORT D PIN

DIR REG.

DQ

WR

Port D – Functionality and Structure

Port D has three I/O pins. See Figure 27 and Fig-

ure 28. This port does not support Address Out

mode, and therefore no Control Register is re-

quired. Port D can be configured to perform one or

more of the following functions:

s MCU I/O Mode

s CPLD Output – External Chip Select (ECS0-

ECS2)

s CPLD Input – direct input to the CPLD, no Input

Macrocells (IMC)

s Slew rate – pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft Express

as input pins for other dedicated functions:

ENABLE PRODUCT

TERM (.OE)

CPLD - INPUT

AI02889

s Address Strobe (ALE/AS, PD0)

s CLKIN (PD1) as input to the macrocells flip-

flops and APD counter

s PSD Chip Select Input (CSI, PD2). Driving this

signal High disables the Flash memory, SRAM

and CSIOP.

External Chip Select

The CPLD also provides three External Chip Se-

lect (ECS0-ECS2) outputs on Port D pins that can

be used to select external devices. Each External

Chip Select (ECS0-ECS2) consists of one product

term that can be configured active High or Low.

The output enable of the pin is controlled by either

the output enable product term or the Direction

Register. (See Figure 28.)

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