PSD834F2V
Table 26. Port Data Registers
Register Name
Port
MCU Access
Data In
A,B,C,D
Read – input on pin
Data Out
A,B,C,D
Write/Read
Output Macrocell
A,B,C
Read – outputs of macrocells
Write – loading macrocells flip-flop
Mask Macrocell
A,B,C
Write/Read – prevents loading into a given
macrocell
Input Macrocell
A,B,C
Read – outputs of the Input Macrocells
Enable Out
A,B,C
Read – the output enable control of the port driver
Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O input mode, the pin in-
put is read through the Data In buffer.
Data Out Register. Stores output data written by
the MCU in the MCU I/O output mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to 1. The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Register bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See the sec-
tion entitled “PLDs”, on page 27.
OMC Mask Register. Each OMC Mask Register
bit corresponds to an Output Macrocell (OMC) flip-
flop. When the OMC Mask Register bit is set to a
1, loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is 0 or un-
blocked.
Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can be read by the
MCU. See the section entitled “PLDs”, on page 27.
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A 1 indicates the driver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.
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