PSD934F210MIT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD934F210MIT
STMicroelectronics
PSD934F210MIT Datasheet PDF : 89 Pages
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PSD834F2V
Figure 20. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
RESET
80C251SB
2
3
4
5
6
7
8
9
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
21 X1
20 X2
11
13 P3.0/RXD
P3.1/TXD
14
P3.2/INT0
15 P3.3/INT1
16 P3.4/T0
17 P3.5/T1
10 RST
35
EA
P0.0 43
P0.1
P0.2
42
41
P0.3 40
P0.4 39
P0.5 38
P0.6 37
P0.7 36
P2.0 24
P2.1 25
P2.2 26
P2.3 27
P2.4 28
P2.5 29
P2.6 30
P2.7 31
ALE 33
32
PSEN
18
WR
19
RD/A16
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ALE
RD
WR
PSEN
RESET
RESET
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PSD
30
31
ADIO0
ADIO1
32 ADIO2
33 ADIO3
34 ADIO4
35 ADIO5
36
37
ADIO6
ADIO7
39
40
ADIO8
ADIO9
41 ADIO10
42
43
ADIO11
ADIO12
44 ADIO13
45 ADIO14
46 ADIO15
47 CNTL0 (WR)
50 CNTL1(RD)
49 CNTL 2(PSEN)
10
9
8
PD0- ALE
PD1
PD2
48
RESET
29
PA0
PA1
28
PA2
27
25
PA3
PA4
PA5
24
23
PA6 22
PA7 21
7
PB0 6
PB1 5
PB2
PB3
PB4
4
3
PB5
PB6
2
52
PB7 51
PC0
PC1
20
19
PC2
PC3
PC4
PC5
PC6
PC7
18
17
14
13
12
11
80C51XA. The Philips 80C51XA MCU family sup-
ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure 21).
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-
AI02882C
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from ad-
dress A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
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