PSD934F210MIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD934F210MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

I/O PORTS

There are four programmable I/O ports: Ports A, B,

C, and D. Each of the ports is eight bits except Port

D, which is 3 bits. Each port pin is individually user

configurable, thus allowing multiple functions per

port. The ports are configured using PSDsoft Ex-

press Configuration or by the MCU writing to on-

chip registers in the CSIOP space.

The topics discussed in this section are:

s General Port architecture

s Port operating modes

s Port Configuration Registers (PCR)

s Port Data Registers

s Individual Port functionality.

General Port Architecture

The general architecture of the I/O Port block is

shown in Figure 23. Individual Port architectures

are shown in Figure 25 to Figure 28. In general,

once the purpose for a port pin has been defined,

Figure 23. General I/O Port Architecture

that pin is no longer available for other purposes.

Exceptions are noted.

As shown in Figure 23, the ports contain an output

multiplexer whose select signals are driven by the

configuration bits in the Control Registers (Ports A

and B only) and PSDsoft Express Configuration.

Inputs to the multiplexer include the following:

s Output data from the Data Out register

s Latched address outputs

s CPLD macrocell output

s External Chip Select (ECS0-ECS2) from the

CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that

allows only one source at a time to be read. The

Port Data Buffer (PDB) is connected to the Internal

Data Bus for feedback and can be read by the

MCU. The Data Out and macrocell outputs, Direc-

tion and Control Registers, and port pin input are

all connected to the Port Data Buffer (PDB).

DATA OUT

REG.

DQ

WR

ADDRESS

ALE

DQ

G

MACROCELL OUTPUTS

EXT CS

READ MUX

P

D

DATA IN

B

CONTROL REG.

DQ

WR

DIR REG.

DQ

WR

ENABLE PRODUCT TERM (.OE)

CPLD - INPUT

DATA OUT

ADDRESS

OUTPUT

MUX

OUTPUT

SELECT

ENABLE OUT

INPUT

MACROCELL

PORT PIN

AI02885

45/89

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