PCA8538UG(2014) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
PCA8538UG Datasheet PDF : 107 Pages
| |||
NXP Semiconductors
PCA8538
Automotive 102 x 9 Chip-On-Glass LCD segment driver
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 39.
6'$
6'$
6&/
6
67$57FRQGLWLRQ
Fig 39. I2C-bus - definition of START and STOP conditions
6&/
6723FRQGLWLRQ
DDD
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 40.
0$67(5
75$160,77(5
5(&(,9(5
6'$
6&/
6/$9(
5(&(,9(5
6/$9(
75$160,77(5
5(&(,9(5
Fig 40. I2C-bus - system configuration
0$67(5
75$160,77(5
0$67(5
75$160,77(5
5(&(,9(5
DDD
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 41.
PCA8538
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
65 of 107
Share Link: 