CS8422-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8422-DNZR Datasheet PDF : 82 Pages
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CS8422
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.
Parameter
Symbol
Min
Max
CCLK Clock Frequency
fsck
0
6.0
RST Rising Edge to CS Falling
tsrs
500
-
CCLK Edge to CS Falling (Note 13)
tspi
500
-
CS High Time Between Transmissions
tcsh
1.0
-
CS Falling to CCLK Edge
tcss
20
-
CCLK Low Time
tscl
66
-
CCLK High Time
tsch
66
-
CDIN to CCLK Rising Setup Time
tdsu
40
-
CCLK Rising to DATA Hold Time (Note 14)
tdh
15
-
CCLK Falling to CDOUT Valid (Note 15)
tscdov
-
100
Time from CS Rising to CDOUT High-Z
tcscdo
-
100
CDOUT Rise Time
tr1
-
25
CDOUT Fall Time
tf1
-
25
CCLK and CDIN Rise Time (Note 16)
tr2
-
100
CCLK and CDIN Fall Time (Note 16)
tf2
-
100
Unit
MHz
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
13. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. CDOUT should not be sampled during this time.
16. For fsck < 1 MHz.
RST
t srs
CS
t spi tcss
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu t dh
Hi-Impedance
t scdov
t scdov
Figure 5. SPI Mode Timing
t cscdo
20
DS692F1
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