CS8422-DNZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8422-DNZR

24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver

Cirrus Logic 

CS8422

DIGITAL INTERFACE SPECIFICATIONS

AGND = DGND = 0 V; all voltages with respect to 0 V.

Parameter

Input Leakage Current (Note 5)

Input Capacitance

Digital Interface Receiver - RXP[1:0], RXN[1:0], RX[3:0]

Differential Input Sensitivity, RXP to RXN (Note 6)

Symbol Min

Iin

-

Iin

-

-

Differential Input Impedance, RXP and RXN to GND

-

Single-Ended Input Sensitivity, RX pins, Receiver Input Mode 1

-

(Note 6)

Single-Ended Input Impedance, RX pins, Receiver Input Mode 1

-

High-Level Input Voltage, RX pins in Digital mode

VIH 0.55xVA

Low-Level Input Voltage, RX pins in Digital mode

Digital I/O

VIL

-0.3

High-Level Output Voltage (IOH = -4 mA)

VOH .77xVL

Low-Level Output Voltage (IOL = 4 mA)

VOL

-

High-Level Input Voltage

VIH 0.65xVL

Low-Level Input Voltage

Input Hysteresis

VIL

-

-

Typ Max

-

+32

8

-

-

200

11

-

-

200

11

-

- VA+0.3

-

0.8

-

-

-

0.6

-

-

- 0.3xVL

0.2

-

Units

A

pF

mVpp

k

mVpp

k

V

V

V

V

V

V

V

Notes:

5.

6.

When a digital signal is sent to the AES RX pins, the pins will draw approximately 730 µA from the digital

signal’s supply from the time RST is released until the RX_MODE, RX_SEL, and INPUT_TYPE bits in

register 03h are properly configured to allow a digital input signal on the driven pins, see Section 11.3

on page 48.

Maximum sensitivity in accordance with AES3-2003 section 8.3.3. Measured with eye diagram height

at the specified voltage and width of at least 50% of one-half the biphase symbol period.

16

DS692F1

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