CS44L11 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS44L11

Low Voltage Class-D PWM Headphone Amplifier

Cirrus Logic 

CS44L11

a 220 µF capacitor and a 16 Ω load on the headphone outputs, the minimum power-down time will be ap-

proximately 0.4 seconds.

Note that ramp-up and ramp-down period can be set to zero with the RUPBYP and RDNBYP bits respec-

tively.

6.5 Recommended Power-Up Sequence

6.5.1

Stand-Alone Mode

1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control

port is reset to its default settings and the HP_x lines will remain low.

2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up

sequence. The control port will be accessible at this time.

6.5.2

Control Port Mode

1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control

port is reset to its default settings and the HP_x lines will remain low.

2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up

sequence. The control port will be accessible at this time.

3. On the CS44L11 the control port pins are shared with stand-alone configuration pins. To enable the

control port, the user must set the CP_EN bit. This is done by performing an I²C write. Once the

control port is enabled, these pins are dedicated to control port functionality.

To prevent audible artifacts, the CP_EN bit (see Section 4.10.4) should be set prior to the completion of

the Stand-Alone power-up sequence (1024/Fs: approximately 21 ms at Fs=48 kHz). Writing this bit will

halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the

CP_EN bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone pow-

er-up sequence has completed can cause audible artifacts.

DS640PP4

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