CS44L11 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS44L11 Datasheet PDF : 34 Pages
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4.9.3
CS44L11
Double-Speed Mode (DBS)
Default = 0
0 - Single-Speed
1 - Double-Speed (DBS)
Function:
Single-Speed supports 8 kHz to 50 kHz sample rates and Double-Speed supports 50 kHz to 96 kHz sam-
ple rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements.
Refer to Tables 11, 12, 13, and Section 6.2.
Note: De-emphasis, ramp control, and treble control are not available in Double-Speed Mode.
4.9.4
Frequency Shift (FRQSFT)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, and Section 6.2.
LRCK
(kHz)
48
48
44.1
44.1
32
32
24
24
12
12
DBS = 0
MCLKDIV = 0
MCLK/
LRCK
256
512
256
512
512
1024
512
1024
1024
2048
MCLK
(MHz)
12.288
24.576
11.2896
22.5792
16.384
32.768
12.288
24.576
12.288
24.576
DBS = 0
MCLKDIV = 1
MCLK/
LRCK
512
1024
512
1024
1024
2048
1024
2048
2048
4096
MCLK
(MHz)
24.576
49.152
22.5792
45.1584
32.768
65.536
24.576
49.152
24.576
49.152
PWM
Switching
Freq.
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0 (kHz)
0
0
0
0
384
0
0
1
0
0
0
0
0
352.8
0
0
1
0
0
1
0
0
512
0
1
1
0
0
1
0
0
384
0
1
1
0
1
0
0
0
384
1
0
1
0
Table 11. Single-Speed Clock Modes - Control Port Mode
LRCK
(kHz)
48
48
44.1
44.1
32
24
12
MCLK/
LRCK
256
512
256
512
1024
1024
2048
MCLK
(MHz)
12.288
24.576
11.2896
22.5792
32.768
24.576
24.576
PWM
Switching
Freq. (kHz)
384
352.8
512
384
Table 12. Single-Speed Clock Modes - Stand-Alone Mode
DS640PP4
21
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