CS44L11
LRCK
(kHz)
96
96
88.2
88.2
DBS = 1
MCLKDIV = 0
MCLK/
LRCK
128
256
128
256
MCLK
(MHz)
12.288
24.576
11.2896
22.5792
DBS = 1
MCLKDIV = 1
MCLK/
LRCK
256
512
256
512
MCLK
(MHz)
24.576
49.152
22.5792
45.1584
FRQSFT1 FRQSFT0
0
0
0
0
0
0
0
0
CLKDIV1
0
1
0
1
PWM
Switching
Freq.
CLKDIV0 (kHz)
0
384
0
0
352.8
0
Table 13. Double-Speed Clock Modes - Control Port Mode
4.9.5
De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates (see Figure 6).
Note: De-emphasis is not available in Double-Speed Mode.
Gain
dB
0dB
T1=50 µs
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 6. De-Emphasis Curve
22
DS640PP4