CS43L42 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L42

4. REGISTER DESCRIPTION

Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.

4.1 Power and Muting Control (address 01h)

7

AMUTE

1

6

SZC1

1

5

SZC0

0

4

POR

1

3

PDNHP

0

2

PDNLN

0

1

PDN

1

0

RESERVED

0

4.1.1 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-

ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is

done independently for each channel. The quiescent voltage on the output will be retained and the Mute

Control pin will go active during the mute period. The muting function is affected, similar to volume control

changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change

01 - Zero Cross Digital and Analog

10 - Ramped Digital and Analog

11 - Reserved

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross Digital and Analog

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a

timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a

zero crossing. The zero cross function is independently monitored and implemented for each channel.

Ramped Digital and Analog

Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally

ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock pe-

riods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change

will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does

not encounter a zero crossing. The zero cross function is independently monitored and implemented for

each channel.

Note: Ramped Digital and Analog is not available in High-Rate Mode.

16

DS481PP2

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