CS43L42 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS43L42 Datasheet PDF : 40 Pages
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CS43L42
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE
(TA = 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
Two-Wire Mode (Note 13)
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 14) thdd
0
-
µs
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL
trc
-
25
ns
Fall Time SCL
tfc
-
25
ns
Rise Time of SDA
trd
1
µs
Fall Time of SDA
tfd
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Notes: 13. The Two-Wire Mode is compatible with the I2C protocol.
14. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
S tart
SDA
SCL
t buf
t hdst
t high
t
lo w
t
hdd
R e pe ate d
S ta rt t rd
t hdst
S to p
t fd
t fc
t susp
t sud
t sust
t rc
Figure 4. Control Port Timing - Two-Wire Mode
12
DS481PP2
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