CS43L42 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS43L42 Datasheet PDF : 40 Pages
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CS43L42
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA = 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
SPI Mode
CCLK Clock Frequency
fsclk
-
6
RST Rising Edge to CS Falling
tsrs
500
-
CCLK Edge to CS Falling
(Note 15)
tspi
500
-
CS High Time Between Transmissions
tcsh
1.0
-
CS Falling to CCLK Edge
tcss
20
-
CCLK Low Time
tscl
66
-
CCLK High Time
tsch
66
-
CDIN to CCLK Rising Setup Time
tdsu
40
-
CCLK Rising to DATA Hold Time
(Note 16)
tdh
15
-
Rise Time of CCLK and CDIN
(Note 17)
tr2
-
100
Fall Time of CCLK and CDIN
(Note 17)
tf2
-
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 15. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
16. Data must be held for sufficient time to bridge the transition time of CCLK.
17. For FSCK < 1 MHz
RST
t srs
CS
t spi t css
t scl t sch
t csh
CCLK
t r2
t f2
C D IN
t dsu t dh
Figure 5. Control Port Timing - SPI Mode
DS481PP2
13
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