CL-PD6833 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PD6833 Datasheet PDF : 216 Pages
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CL-PD6833
PCI-to-CardBus Host Adapter
13.10 Mode Register
Register Name: Mode Register
I/O Index: Bh
Bit 7
Bit 6
Bit 5
Request Mode
Address
Decrement
R/W:00
R/W:0
Bit 4
Autoinitialize
R/W:0
Register Per: socket
Register Compatibility Type: DMA
Bit 3
Bit 2
Bit 1
Bit 0
Transfer Mode
Channel Number
(Ignored)
R/W:00
R/W:00
This register emulates the mode register of the Intel 8237. Unlike the Intel 8237 mode register, this register
is readable.
Bits 1:0 — Channel Number (Ignored)
Writes to these bits have no effect. These bits read back what was written to them.
Bits 3:2 — Transfer Mode
These two bits determine the transfer mode to be used.
Bit 3
0
0
1
1
Bit 2
0
1
0
1
Verify mode
DMA write
DMA read
Reserved
Transfer Mode
Bit 4 — Autoinitialize
This bit puts the DMA controller in auto-initialize mode. In this mode the current address and count
registers are reloaded from the Base registers. This sets the DMA controller for a new transfer at
the end of the current transfer.
Bit 5 — Address Decrement
If this bit is set the addresses generated proceed downward from the base address until the count
is exhausted. If this bit is reset, the addresses generated increment until the end of transfer.
Bits 7:6 — Request Mode
These two bits determine the request mode to be used.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Request Mode
Demand mode
Single Transfer mode
Block mode select
Cascade mode (not implemented)
June 1998
ADVANCE DATA BOOK v0.3
DMA OPERATION REGISTERS
177
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