C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable

and re-enable) the SMBus in the event of an SCL low timeout.

18.3.4. SCL High (SMBus Free) Timeout

The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus

is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and

SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a

Master START, the START will be generated following this timeout. Note that a clock source is required for

free timeout detection, even in a slave-only implementation.

18.4. Using the SMBus

The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-

trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides

the following application-independent features:

• Byte-wise serial data transfers

• Clock signal generation on SCL (Master Mode only) and SDA data synchronization

• Timeout/bus error recognition, as defined by the SMB0CF configuration register

• START/STOP timing, detection, and generation

• Bus arbitration

• Interrupt generation

• Status information

SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,

this interrupt is generated after the ACK cycle so that software may read the received ACK value; when

receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing

ACK value. See Section “18.5. SMBus Transfer Modes” on page 213 for more details on transmission

sequences.

Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or

the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control

register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section

“18.4.2. SMB0CN Control Register” on page 209; Table 18.4 provides a quick SMB0CN decoding refer-

ence.

SMBus configuration options include:

• Timeout detection (SCL Low Timeout and/or Bus Free Timeout)

• SDA setup and hold time extensions

• Slave event enable/disable

• Clock source selection

These options are selected in the SMB0CF register, as described in Section “18.4.1. SMBus Configuration

Register” on page 206.

Rev. 1.0

205

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