C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

Bit

MASTER

TXMODE

STA

STO

ACKRQ

ARBLOST

ACK

SI

Table 18.3. Sources for Hardware Changes to SMB0CN

Set by Hardware When:

Cleared by Hardware When:

• A START is generated.

• A STOP is generated.

• Arbitration is lost.

• START is generated.

• SMB0DAT is written before the start of an

SMBus frame.

• A START is detected.

• Arbitration is lost.

• SMB0DAT is not written before the

start of an SMBus frame.

• A START followed by an address byte is

received.

• Must be cleared by software.

• A STOP is detected while addressed as a

slave.

• A pending STOP is generated.

• Arbitration is lost due to a detected STOP.

• A byte has been received and an ACK

response value is needed.

• After each ACK cycle.

• A repeated START is detected as a MASTER

when STA is low (unwanted repeated START).

• SCL is sensed low while attempting to gener-

ate a STOP or repeated START condition.

• Each time SI is cleared.

• SDA is sensed low while transmitting a ‘1’

(excluding ACK bits).

• The incoming ACK value is low

• The incoming ACK value is high (NOT

(ACKNOWLEDGE).

ACKNOWLEDGE).

• A START has been generated.

• Lost arbitration.

• A byte has been transmitted and an

ACK/NACK received.

• A byte has been received.

• Must be cleared by software.

• A START or repeated START followed by a

slave address + R/W has been received.

• A STOP has been received.

Rev. 1.0

211

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