C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 17.14. P1MASK: Port1 Mask

SFR Page: 0

SFR Address: 0xE2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: P1MASK[7:0]: Port1 Mask Value.

These bits select which Port pins will be compared to the value stored in P1MAT.

0: Corresponding P1.n pin is ignored and cannot cause a Port Match event.

1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT.

SFR Definition 17.15. P2: Port2

SFR Page: all pages

SFR Address: 0xA0

R/W

R/W

P2.7

P2.6

Bit7

Bit6

(bit addressable)

R/W

P2.5

Bit5

R/W

P2.4

Bit4

R/W

P2.3

Bit3

R/W

P2.2

Bit2

R/W

P2.1

Bit1

R/W

P2.0

Bit0

Reset Value

11111111

Bits 7–0: P2.[7:0]

Write - Output appears on I/O pins per Crossbar Registers.

0: Logic Low Output.

1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).

Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port

pin when configured as digital input.

0: P2.n pin is logic low.

1: P2.n pin is logic high.

Rev. 1.0

195

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