C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F362-GM2 Datasheet PDF : 288 Pages
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C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 16.8. PLL0MUL: PLL Clock Scaler
SFR Page: F
SFR Address: 0xB1
R/W
R/W
PLLN7 PLLN6
Bit7
Bit6
R/W
PLLN5
Bit5
R/W
PLLN4
Bit4
R/W
PLLN3
Bit3
R/W
PLLN2
Bit2
R/W
PLLN1
Bit1
R/W
PLLN0
Bit0
Reset Value
00000001
Bits 7–0: PLLN7–0: PLL Multiplier.
These bits select the multiplication factor of the divided PLL reference clock. When set to
any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set
to ‘00000000b’, the multiplication factor will be equal to 256.
SFR Definition 16.9. PLL0FLT: PLL Filter
SFR Page: F
SFR Address: 0xB2
R/W
R/W
–
–
Bit7
Bit6
R/W
R/W
PLLICO1 PLLICO0
Bit5
Bit4
R/W
PLLLP3
Bit3
R/W
PLLLP2
Bit2
R/W
PLLLP1
Bit1
R/W
PLLLP0
Bit0
Reset Value
00110001
Bits 7–6: UNUSED. Read = 00b. Write = don’t care.
Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:
PLL Output Clock
65–100 MHz
45–80 MHz
30–60 MHz
25–50 MHz
PLLICO1-0
00
01
10
11
Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:
Divided PLL Reference Clock
19–30 MHz
12.2–19.5 MHz
7.8–12.5 MHz
5–8 MHz
PLLLP3-0
0001
0011
0111
1111
All other states of PLLLP3–0 are RESERVED.
Rev. 1.0
181
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