C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 17.9. P1: Port1

SFR Page: all pages

SFR Address: 0x90

R/W

R/W

P1.7

P1.6

Bit7

Bit6

(bit addressable)

R/W

P1.5

Bit5

R/W

P1.4

Bit4

R/W

P1.3

Bit3

R/W

P1.2

Bit2

R/W

P1.1

Bit1

R/W

P1.0

Bit0

Reset Value

11111111

Bits 7–0: P1.[7:0]

Write - Output appears on I/O pins per Crossbar Registers.

0: Logic Low Output.

1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).

Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port

pin when configured as digital input.

0: P1.n pin is logic low.

1: P1.n pin is logic high.

SFR Definition 17.10. P1MDIN: Port1 Input Mode

SFR Page: F

SFR Address: 0xF2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: Analog Input Configuration Bits for P1.7-P1.0 (respectively).

Port pins configured as analog inputs have their weak pullup, digital driver, and digital

receiver disabled.

0: Corresponding P1.n pin is configured as an analog input.

1: Corresponding P1.n pin is not configured as an analog input.

Rev. 1.0

193

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