C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

13. RESET SOURCES

The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry

to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes

the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is

reset, and program execution starts at location 0x0000.

All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR detailed

descriptions. The contents of internal data memory are not changed during a reset and any previously stored data is

preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the

stack are not altered.

The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the external I/O

pins to a high state. The weak pull-ups are enabled during and after the reset. If the source of reset is from the VDD

Monitor or writing a 1 to PORSF, the /RST pin is driven low until the end of the VDD reset timeout.

On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by default.

Refer to Section 14 for information on selecting and configuring the system clock source. The Watchdog Timer is

enabled using its longest timeout interval. (Section 13.8 details the use of the Watchdog Timer.)

There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external

CNVSTR signal, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset

source is described below:

Figure 13.1. Reset Sources Diagram

VDD

(Port

I/O)

CP0+

CP0-

Crossbar

CNVSTR

CNVRSEF

Comparator 0

+

-

C0RSEF

System

Clock

Missing

Clock

Detector

(one-

shot)

EN

WDT

EN PRE

Supply

Monitor

+

-

Supply

Reset

Timeout

(wired-OR)

(Software Reset)

SWRSF

CIP-51 System Reset

Core

Reset

Funnel

/RST

93

Rev. 1.7

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