C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 17.7. SPI0CKR: SPI Clock Rate Register

R/W

SCR7

Bit7

R/W

SCR6

Bit6

R/W

SCR5

Bit5

R/W

SCR4

Bit4

R/W

SCR3

Bit3

R/W

SCR2

Bit2

R/W

SCR1

Bit1

R/W

SCR0

Bit0

Reset Value

00000000

SFR Address:

0x9D

Bits7-0: SCR7-SCR0: SPI Clock Rate

These bits determine the frequency of the SCK output when the SPI module is

configured for master mode operation. The SCK clock frequency is a divided down

version of the system clock, and is given in the following equations:

fSCK = 0.5 * fSYSCLK / (SPI0CKR + 1),

for 0 ≤ SPI0CKR ≤ 255,

Figure 17.8. SPI0DAT: SPI Data Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x9B

Bits7-0: SPI0DAT: SPI0 Transmit and Receive Data.

The SPI0DAT register is used to transmit and receive SPI data. Writing data to SPI0DAT

places the data immediately into the shift register and initiates a transfer when in Master

Mode. A read of SPI0DAT returns the contents of the receive buffer.

129

Rev. 1.7

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