C8051F007 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F007 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
17. SERIAL PERIPHERAL INTERFACE BUS
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports the
connection of multiple slave devices to a master device on the same bus. A separate slave-select signal (NSS) is
used to select a slave device and enable a data transfer between the master and the selected slave. Multiple masters
on the same bus are also supported. Collision detection is provided when two or more masters attempt a data
transfer at the same time. The SPI can operate as either a master or a slave. When the SPI is configured as a
master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the
system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer
rate (bits/sec) must be less that 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave
can receive data at a maximum data transfer rate (bits/sec) of ¼ the system clock frequency. This is provided that
the master issues SCK, NSS, and the serial input data synchronously with the system clock.
Figure 17.1. SPI Block Diagram
SFR Bus
SPI0CKR
SSSSSSSS
CCCCCCCC
RRRRRRRR
76543210
SPI0CFG
CCBBBF F F
KKCCCRRR
PP2 1 0SSS
HO
210
AL
SPI0CN
SWMR T S M S
PCOXX L SP
I ODOBV T I
F L FVSSEE
RYENN
NL
SYSCLK
Clock Divide
Logic
Bit Count
Logic
SPI CONTROL LOGIC
Data Path
Control
SPI Clock
(Master Mode)
Pin Control
Interface
SPI IRQ
SCK
C
Tx Data
MOSI R
O
SPI0DAT
Shift Register
76543210
Rx Data
Pin
Control
Logic
MISO
S
S
B
A
R
Receive Data Register
NSS
Write to
SPI0DAT
Read
SPI0DAT
SFR Bus
Port I/O
123
Rev. 1.7
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