C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 17.6. SPI0CN: SPI Control Register

R/W

SPIF

Bit7

R/W

WCOL

Bit6

R/W

MODF

Bit5

R/W

RXOVRN

Bit4

R

TXBSY

Bit3

R

SLVSEL

Bit2

R/W

MSTEN

Bit1

R/W

SPIEN

Bit0

(bit addressable)

Reset Value

00000000

SFR Address:

0xF8

Bit7:

SPIF: SPI Interrupt Flag.

This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,

setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is

not automatically cleared by hardware. It must be cleared by software.

Bit6:

WCOL: Write Collision Flag.

This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to

the SPI data register was attempted while a data transfer was in progress. It is cleared by

software.

Bit5:

MODF: Mode Fault Flag.

This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode

collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by

hardware. It must be cleared by software.

Bit4:

RXOVRN: Receive Overrun Flag.

This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive

buffer still holds unread data from a previous transfer and the last bit of the current transfer

is shifted into the SPI shift register. This bit is not automatically cleared by hardware. It

must be cleared by software.

Bit3:

TXBSY: Transmit Busy Flag.

This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is

cleared by hardware at the end of the transfer.

Bit2:

SLVSEL: Slave Selected Flag.

This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It

is cleared to logic 0 when NSS is high (slave disabled).

Bit1:

MSTEN: Master Mode Enable.

0: Disable master mode. Operate in slave mode.

1: Enable master mode. Operate as a master.

Bit0:

SPIEN: SPI Enable.

This bit enables/disables the SPI.

0: SPI disabled.

1: SPI enabled.

Rev. 1.7

128

Share Link: