C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

16.6.2. Clock Rate Register

Figure 16.5. SMB0CR: SMBus Clock Rate Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xCF

Bits7-0: SMB0CR.[7:0]: SMBus Clock Rate Preset

The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master

mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer.

The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.

The SMB0CR setting should be bounded by the following equation, where SMB0CR is the

unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in

Hz:

SMB0CR < ((288 - 0.85 * SYSCLK) / 1.125E6)

The resulting SCL signal high and low times are given by the following equations:

TLOW = (256 – SMB0CR) / SYSCLK

THIGH ≅ (258 – SMB0CR) / SYSCLK + 625 ns

Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the

following equation:

TBFT ≅ 10 * [(256 – SMB0CR) + 1] / SYSCLK

119

Rev. 1.7

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