C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 15.13. P3: Port3 Register

R/W

P3.7

Bit7

R/W

P3.6

Bit6

R/W

P3.5

Bit5

R/W

P3.4

Bit4

R/W

P3.3

Bit3

R/W

P3.2

Bit2

R/W

P3.1

Bit1

R/W

P3.0

Bit0

(bit addressable)

Reset Value

11111111

SFR Address:

0xB0

Bits7-0: P3.[7:0]

(Write)

0: Logic Low Output.

1: Logic High Output (high-impedance if corresponding PRT3CF.n bit = 0)

(Read)

0: P3.n is logic low.

1: P3.n is logic high.

Figure 15.14. PRT3CF: Port3 Configuration Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits7-0: PRT3CF.[7:0]: Output Configuration Bits for P3.7-P3.0 (respectively)

0: Corresponding P3.n Output mode is Open-Drain.

1: Corresponding P3.n Output mode is Push-Pull.

Reset Value

00000000

SFR Address:

0xA7

Table 15.2. Port I/O DC Electrical Characteristics

VDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specified.

PARAMETER

CONDITIONS

Output High Voltage

IOH = -10uA, Port I/O push-pull

IOH = -3mA, Port I/O push-pull

IOH = -10mA, Port I/O push-pull

Output Low Voltage

Input High Voltage

IOL = 10uA

IOL = 8.5mA

IOL = 25mA

Input Low Voltage

MIN

VDD –

0.1

VDD –

0.7

TYP

VDD –

0.8

1.0

0.7 x

VDD

Input Leakage Current

DGND < Port Pin < VDD, Pin Tri-state

Weak Pull-up Off

Weak Pull-up On

30

Capacitive Loading

5

MAX

0.1

0.6

0.3 x

VDD

±1

UNITS

V

V

V

V

µA

pF

Rev. 1.7

112

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