C8051F007 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F007 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16. SMBus / I2C Bus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I2C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is used to accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of
data transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave.
Multiple master devices on the same bus are also supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
Figure 16.1. SMBus Block Diagram
SFR Bus
SMB0CN
BESSSAFT
UNT T I ATO
S S AO
EE
YM
B
SMB0STA
SSSSSSSS
TTTTTTTT
AAAAAAAA
76543210
SMB0CR
CCCCCCCC
RRRRRRRR
76543210
Clock Divide
Logic
SYSCLK
SMBUS
IRQ
Interrupt
Request
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
Data Path
Control
SCL
Control
SDA
Control
BA
BA
7
SSSSSSS
LLLLLLL
V V V V V V VG
6 5 4 3 2 1 0C
SMB0ADR
0000000b
7 MSBs
8
SMB0DAT
76543210
8
Read
SMB0DAT
8
1
0
Write to
SMB0DAT
FILTER
SCL
N
C
R
O
S
S
B
A
R
FILTER
SDA
N
SFR Bus
Port I/O
113
Rev. 1.7
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