ACS8522AT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Figure 10 PLL Block Diagram
FINAL
T4
Reference
Input
SEC1
SEC2
SEC3
SEC4
Lock_T4_to_T0
Control
Sts_Current_Phase
T4_DPLL_Frequency
0
PFD and
Forward
Loop Filter
DFS T4_Dig_Feedback
1
T0_DPLL_Freq
1
0
Feedback
Locking
DFS
0
T4 DPLL
Frequency
1
T4_APLL_for_T0
0
1
T0
Reference
Input
SEC1
SEC2
SEC3
SEC4
8 kHz
Sts_Current_Phase
77M
Output
1
DFS
Phase 0
PBO Offset
LF
Output
DFS
T0_DPLL_Frequency
Control
0
1
PFD and
Loop Filter
77M
Forward
DFS
T0_DPLL_Frequency
Control
1
Feedback
Locking
DFS
Frequency
0
T0 DPLL
T4
Output
APLL
T0
Output
APLL
T0
Feedback
APLL
DATASHEET
T4
Output
Dividers
O1, O2
O3, O4
T0
Output
Dividers
O1, O2
O3, O4
O1, O2
O3, O4
FrSync
MFrSync
Analog
F8522D_017BLOCKDIA_01
The T4 output APLL block is also for multiplying and
filtering. The input to the T4 output APLL can come either
from the T4 forward DFS block or from the T0 path. The
input to the T4 output APLL can be programmed to be one
of the following:
(a) Output from the T4 forward DFS block (12E1, 24DS1,
16E1, 16DS1, E3, DS3, OC-N),
(b) 12E1 from T0,
(c) 16E1 from T0,
(d) 24DS1 from T0,
(e) 16DS1 from T0.
The frequency generated from the T4 output APLL block is
four times its input frequency i.e. 311.04 MHz when used
with a 77.76 MHz input. The T4 output APLL is
subsequently divided by 2, 4, 8, 12, 16, 48 and 64 and
these are available at the O1 to O4 outputs.
The outputs O1 to O4 are driven from either the T4 or the
T0 path. The FrSync and MFrSync outputs are always
generated from the T0 path. Reg.7A bit 7 selects whether
the source of the 2 kHz and 8 kHz outputs available from
O1 to O4 is derived from either the T0 or the T4 paths.
Output Frequency Configuration Steps
The output frequency selection is performed in the
following steps:
1. Does the application require the use of the T4 path as
an independent PLL path or not. If not, then the T4
path can be utilized to produce extra frequencies
locked to the T0 path.
2. Refer to Table 13, Frequency Divider Look-up, to
choose a set of output frequencies- one for each path,
T4 and T0. Only one set of frequencies can be
generated simultaneously from each path.
3. Refer to the Table 13 to determine the required APLL
frequency to support the frequency set.
4. Refer to Table 14, T0 APLL Frequencies, and
Table 15, T4 APLL Frequencies, to determine what
mode the T0 and T4 paths need to be configured in,
considering the output jitter level.
5. Refer to Table 16, O1 to O4 Output Frequency
Selection, and the column headings in Table 13,
Frequency Divider Look-up, to select the appropriate
frequency from either of the APLLs on each output as
required.
Revision 1.00/September 2007 © Semtech Corp.
Page 29
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