ACS8522AT View Datasheet(PDF) - Semtech Corporation
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MFG CO.
ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Output Frequency Selection and Configuration
The output frequency of outputs O1 to O4 is controlled by
a number of interdependent parameters. These
parameters control the selections within the various
blocks shown in Figure 10.
The ACS8522A contains two main DPLL/APLL paths, T0
and T4. Whilst they are largely independent, there are a
number of ways in which these two structures can
interact. Figure 10 is an expansion of the top level Block
Diagram (Figure 1) showing the PLL paths in more detail.
T0 DPLL and APLLs
The T0 DPLL always produces 77.76 MHz regardless of
either the reference frequency (frequency at the input pin
of the device) or the locking frequency (frequency at the
input of the DPLL Phase and Frequency Detector (PFD)).
The input reference is either passed directly to the PFD or
via a pre-divider (not shown) to produce the reference
input. The feedback 77.76 MHz is either divided or
synthesized to generate the locking frequency.
Digital Frequency Synthesis (DFS) is a technique for
generating an output frequency using a higher frequency
system clock (204.8 MHz in the case of the 77.76 MHz
synthesis). However, the edges of the output clock are not
ideally placed in time, since all edges of the output clock
will be aligned to the active edge of the system clock. This
will mean that the generated clock will inherently have
DFS and the T0 77M output DFS blocks are locked in
frequency but may be offset in phase.
The T0 77M output DFS block also uses the 204.8 MHz
system clock and always generates 77.76 MHz for the
output clocks (with inherent 4.9 ns of jitter). This is fed to
another DFS block and to the T0 output APLL. The low
frequency T0 LF output DFS block is used to produce
three frequencies; two of them, Digital1 and Digital2, are
available for selection to be produced at outputs O1 to
O4, and the third frequency can produce multiple E1/DS1
rates via the filtering APLLs. The input clock to the T0 LF
output DFS block is either 77.76 MHz from the T0 output
APLL (post jitter filtering) or 77.76 MHz direct from the T0
77M output DFS. Utilizing the clock from the T0 output
APLL will result in lower jitter outputs from the T0 LF
output DFS block. However, when the input to the T0 APLL
is taken from the T0 LF output DFS block, the input to that
block comes directly from the T0 77M output DFS block
so that a “loop” is not created.
The T0 output APLL is for multiplying and filtering. The
input to the T0 output APLL can be either 77.76 MHz from
the T0 77M output DFS block or an alternative frequency
from the T0 LF output DFS block (offering 77.76 MHz,
12E1, 16E1, 24DS1 or 16DS1). The frequency from the
T0 output APLL is four times its input frequency i.e.
311.04 MHz when used with a 77.76 MHz input. The T0
output APLL is subsequently divided by 1, 2, 4, 6, 8, 12,
16 and 48 and these are available at the O1 to O4
outputs.
jitter on it equivalent to one period of the system clock. T4 DPLL & APLL
The T0 77M forward DFS block uses DFS clocked by the
204.8 MHz system clock to synthesize the 77.76 MHz
and, therefore, has an inherent 4.9 ns of pk-pk jitter.
There is an option to use an APLL, the T0 feedback APLL,
to filter out this jitter before the 77.76 MHz is used to
generate the feedback locking frequency in the T0
feedback DFS block. This analog feedback option allows
a lower jitter (<1 ns) feedback signal to give maximum
performance. The digital feedback option is present so
that when the output path is switched to digital feedback
the two paths remain synchronized.
The T0 77M forward DFS block is also the block that
handles Phase Build-out and any phase offset
programmed into the device. Hence, the T0 77M forward
The T4 path is much simpler than the T0 path. This path
offers no Phase Build-out or phase offset. The T4 input
can be used to either lock to a reference clock input
independent of the T0 path, or lock to the T0 path. Unlike
the T0 path, the T4 forward DFS block does not always
generate 77.76 MHz. The possible frequencies are listed
in the table. Similar to the T0 path, the output of the T4
forward DFS block is generated using DFS clocked by the
204.8 MHz system clock and will have an inherent jitter of
4.9 ns.
The T4 feedback DFS also has the facility to be able to use
the post T4 APLL (jitter-filtered) clock to generate the
feedback locking frequency. Again, this will give the
maximum performance by using a low jitter feedback.
Revision 1.00/September 2007 © Semtech Corp.
Page 28
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