CL-PS7500FE
System-on-a-Chip for Internet Appliance
SCLK
ts c k l
ts c k h
Figure 22-30. Sound Clock Timing
ECLK
ED[7:0]
tl c d e d
te c l k
Figure 22-31. Timing Relationship Between ECLK and ED in LCD Grayscale Mode
ECLK
te d
ED[7:0]
Figure 22-32. Timing Relationship Between ECLK and ED in All Other Modes
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ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v2.0
June 1997