CL-PS7500FE
System-on-a-Chip for Internet Appliance
CPUCLK
MEMCLK
I_OCLK
tc p c k 1 l
tm c k 1 l
tc p c k 1 h
tm c k 1 l
ti o c k 1 l
ti o c k 1 l
Figure 22-27. Clock Timing with Divide-by-1 Prescalars Selected
CPUCLK
MEMCLK
I_OCLK
tc p c k 2 l
tm c k 2 l
tc p c k 2 h
tm c k 2 l
ti o c k 2 l
ti o c k 2 l
Figure 22-28. Clock Timing with Divide-by-2 Prescalars Selected
VCLKI
HCLK
t vckl
th c k l
tv c k h
th c k h
Figure 22-29. Video Clock Timing
June 1997
ADVANCE DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
223