ACS411CS View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS411CS Datasheet PDF : 43 Pages
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uP Interface timing - SERIAL mode
In SERIAL mode, the device is configured to interface
with a serial microprocessor bus. The following
figures show the timing diagrams of write and read
accesses for this mode.
During read access the output data sdo (AD(0)) is
clocked out on the rising edge of SCLK (ALE) when
the active edge selection control bit CLKE (A(1)) is
0, and on the falling edge when CLKE is 1. Address,
read/write control bit and write data are always
clocked into the interface on the rising edge of SCLK.
Both input data sdi and clock SCLK are oversampled
, filtered and synchronized to the system clock CLKX.
The serial interface clock (SCLK) is not required to
run when no access is performed (CSB = 1).
CSB
ALE = SCLK
A(0) = SDI
tsu2
th1
tsu1
R/W
AD(0) = SDO
tpw2
tpw1
A1 A2 A3 A4 A5 A6
Z
th2
td1
D0 D1 D2 D3 D4 D5 D6
td2
Z
Symbol
Parameter
Min
tsu1 Setup SDI valid to SCLK ↑
10 *
tsu2 Setup CSB ↓ to SCLK ↑
10 *
th1 Hold SDI to SCLK ↑
10 *
th2 Hold SCLK ↑ to CSB ↑
10 *
tpw1 SCLK low time
240
tpw2 SCLK high time
240
td1
Delay SCLK ↑ (SCLK ↓ for
CLKE = 1) to SDO valid
td2 Delay CSB ↑ to SDO High-Z
tp
Time between consecutive accesses
(CSB ↑ to CSB ↓ )
250
Typ Max
20 *
120
Figure 10: Read access timing in SERIAL Mode.
Note: preliminary timing information. Timing values marked with * TBA.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
20
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