CSB
WRB
RDB
A
AD
RDY
tsu1
tsu2
tpw1
th2
th1
address
tsu3
th4
td1
Z
data
td2
tpw2
th3
td3
Z
Symbol
Parameter
Min
tsu1 Setup A valid to CSB ↓
0
tsu2 Setup CSB ↓ to WRB ↓
0
tsu3 Setup D valid to WRB ↑
10 *
td1 Delay CSB ↓ to RDY active
td2 Delay WRB ↓ to RDY ↓
td3 Delay CSB ↑ to RDY High-Z
tpw1 WRB low time
60
tpw2 RDY low time
20
th1 Hold A valid after WRB ↑
5*
th2 Hold CSB low after WRB ↑
0
th3 Hold WRB low after RDY ↑
0
th4 AD hold valid after WRB ↑
5*
Time between consecutive accesses
tp (WRB ↑ to WRB ↓ or WRB ↑ to
60
RDB ↓)
Typ Max
10 *
10 *
10 *
60
Figure 7: Write access timing in INTEL Mode.
Note: preliminary timing information. Timing values marked with * TBA.
17
ACS411CS PRE-RELEASE Issue 6.0 July 1999.