QL82SD-PB516 数据手册 ( 数据表 ) - QuickLogic Corporation

General Description
LVDS SERDES Transmitter and Receiver
A QuickSD LVDS SERDES device in serializer mode takes a parallel data bus and a separate clock and converts them into a serial data stream. In deserializer mode, it takes a serial data stream and converts it to a configurable bit wide parallel data bus and separate clock. The reduced number of I/O board traces and cable connectors saves on cost and significantly simplifies design. Skew and timing issues are significantly reduced and performance is enhanced. Figure 2 and Figure 3 illustrate the block diagrams of the QuickSD device transmitter and receiver.

Device Highlights
LVDS SERDES Basic Features
• 10 High Speed Bus LVDS Serial Links—bandwidth up to 5 Gbps
• Eight Independent Bus LVDS serial transceivers with operating speeds to 632 Mbps per channel
• Two Independent Bus LVDS clock serial transceivers with operating speeds to 400 MHz per channel
• Integrated clock and data recovery (CDR) with no external analog components required
• CDR bypass for applications with external clock source
• Programmable serial to parallel configuration
• 10-bit data width—with
• clock recovery
• 4-bit, 7-bit and 8-bit data widths— with external clock
• 1-bit asynchronous level conversion
• Fast Lock and Random (auto) Lock capable
• Lock signal feedback
• I/O support for LVTTL, LVCMOS, PCI, GTL+, SSTL2, SSTL3, LVDS, LVPECL
• Low Power/Independent power-down mode for each SERDES channel
• IEEE1149.1 JTAG Support & boundary scan
• Operation over PCB or backplane traces, or across twisted pair cabling up to 25 m
• Point-to-Point, Multi-Point, and Multi-Drop Support
• Pre-Emphasis Control on each LVDS Channel Link

Extended Features
The following can be implemented into the programmable logic:
• UTOPIA Level 2, 16-bit wide System interface (up to 50 MHz) with parity support for ATM applications
• UTOPIA Level 3 compatible 8-bit wide system Interface (up to 100 MHz) with parity support for ATM applications
• CSIX-L1 32-bit switch fabric interface (up to 100 MHz)
• Supports Generic 8,16,32-bit microprocessor bus interface for configuration, control and status monitoring
• Supports Generic 32, 64-bit peripheral bus interface for bridging functions

Flexible Programmable Logic
• 2,016 Programmable Logic Cells
• 536 K System Gates
• Muxed architecture; non-volatile technology
• Completely customizable for any digital application

Dual Port SRAM Blocks
• 36 Dual Port SRAM Blocks
• Configurable array sizes (by 2, 4, 9, 18)
• < 3 ns access times, FIFO capable of over 300 MHz
• Configurable as RAM or FIFO

Programmable I/O
• Up to 252 Programmable I/O pins
• High performance Enhanced I/O (EIO): Less than 3 ns Tco
• Programmable Slew Rate Control
• Programmable I/O Standards
• LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3, LVDS, LVPECL
• Four Independent I/O Banks
• Three Register Configuration: Input, Output, OE

Embedded Computational Unit (ECU) Blocks
• Integrated multiply, add, and accumulate function
• 18 distributed MAC blocks
• 8 × 8 multiply (sign & unsigned)
• 16-bit carry add

Advanced Clock Network
• Nine Global Clock Networks consisting of:
   • one dedicated
   • eight programmable
• Eight I/O (high drive) networks: two I/Os per bank
• Ten Quad-Net Networks—five per quadrant