JS28F128P30T85A 数据手册 ( 数据表 ) - Numonyx -> Micron

Overview
   This section provides an overview of the features and capabilities of the P30.

   The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

   Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the Read Configuration Register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a usersupplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization.