CS2000-CP 数据手册 ( 数据表 ) - Cirrus Logic

The CS2000-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2000-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for both frequency synthesis/clock generation from a stable reference clock as well as generation of a low jitter clock relative to an external noisy synchronization clock. The design is also unique in that it can generate low-jitter clocks relative to noisy external synchronization clocks at frequencies as low as 50 Hz. The CS2000-CP supports both I²C and SPI for full software control.

FEATUREs
♦ Delta-Sigma Fractional-N Frequency Synthesis
   – Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock
♦ Clock Multiplier / Jitter Reduction
   – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source
♦ Highly Accurate PLL Multiplication Factor
   – Maximum Error Less Than 1 PPM in High Resolution Mode
♦ I²C / SPI™ Control Port
♦ Configurable Auxiliary Output
♦ Flexible Sourcing of Reference Clock
   – External Oscillator or Clock Source
   – Supports Inexpensive Local Crystal
♦ Minimal Board Space Required
   – No External Analog Loop-filter Components