CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

APPLICATION NOTE: As a result of the PC ar-

chitecture, DMA cannot occur across a 128K

boundary in memory. Thus, the DMA buffer re-

served for the CS8900 must not cross a 128K

boundary in host memory if DMA operation is

desired. Requesting a 64K, rather than a 16K

buffer, increases the probability of crossing a

128K boundary. After the driver requests a DMA

buffer, the driver must check for a boundary

crossing. If the boundary is crossed, then the

driver must disable DMA functionality.

5.4.4 Receive-DMA-Only Operation

If space is available, an incoming frame is tem-

porarily stored in on-chip RAM. When the entire

frame has been received, pre-processed, and ac-

cepted, the CS8900 signals the DMA controller

that a frame is to be transferred to host memory

by driving the selected DMA Request pin high.

The DMA controller acknowledges the request

by driving the DMA Acknowledge pin low. The

CS8900 then transfers the contents of the

RxStatus register (PacketPage base + 0400h) and

the RxLength register (PacketPage base + 0402h)

to host memory, followed by the frame data. If

the DMABurst bit (Register 17, BusCTL, Bit B)

is clear, the DMA Request pin remains high until

the entire frame is transferred. If the DMABurst

bit is set, the DMA Request pin (DMARQ) re-

mains high for approximately 28 µs then goes

low for approximately 1.3 µs to give the CPU

and other peripherals access to the bus.

When the transfer is complete, the CS8900 does

the following:

• updates the DMA Start-of-Frame register

(PacketPage base + 0026h);

• updates the DMA Frame Count register

(PacketPage base + 0028h);

• updates DMA Byte Count register (Packet-

Page base + 002Ah);

90

• sets the RxDMAFrame bit (Register C,

BufEvent, Bit 7); and,

• de-allocates the buffer space used by the

transferred frame.

In addition, if the RxDMAiE bit (Register B,

BufCFG, Bit 7) is set, a corresponding interrupt

occurs.

When the host processes DMAed frames, it must

read the DMA Frame Count register.

Whenever a receive frame is missed (lost) due to

insufficient receive buffer space, the RxMISS

counter (Register 10) is incremented. A missed

receive frame causes the counter to increment in

either DMA or non-DMA modes.

Note that when in DMA mode, reading the con-

tents of the RxEvent register will return 0000h.

Status information should be obtained from the

DMA buffer.

5.4.5 Committing Buffer Space to a DMAed

Frame

Although a receive frame may occupy space in

the host memory’s circular DMA buffer, the

CS8900’s Memory Manager does not commit the

buffer space to the receive frame until the entire

frame has been transferred and the host learns of

the frame’s existence by reading the Frame

Count register (PacketPage base + 0028h).

When the CS8900 commits DMA buffer space to

a particular DMAed receive frame (termed a

committed received frame), no data from sub-

sequent frames can be written to that buffer

space until the committed received frame is freed

from commitment. (The committed received

frame may or may not have been received error

free.)

DS150PP2

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