CS8900-CQ 查看數據表（PDF） - Cirrus Logic
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CS8900-CQ Datasheet PDF : 132 Pages
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CS8900
Register 17: Bus Control (BusCTL, Read/Write)
Address: PacketPage base + 0116h
F
E
D
C
B
A
9
8
EnableIRQ
RxDMA
size
IOCH DMABurst MemoryE UseSA
RDYE
BusCTL controls the operation of the ISA-bus interface.
7
6
5-0
Reset
RxDMA
010111
BIT NAME
DESCRIPTION
5-0 010111
These bits provide an internal address used by the CS8900 to identify this as the Bus
Control Register. To write to this register, these bits must be 010111, where the LSB
corresponds to Bit 0.
6
ResetRxDMA When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero.
When the host sets this bit, the CS8900 does the following:
1. Terminates the current receive DMA activity, if any.
2. Clears all internal receive buffers.
3. Zeroes the RxDMA offset pointer.
The CS8900 acts upon this command only once when this bit is set. ResetRxDMA is
an Act-Once bit. To cause the pointer to reset again, the host must re-write a "1".
9
UseSA
When set, the MEMCS16 pin goes low whenever the address on the SA bus [13..19]
match the CS8900’s assigned Memory base address and the CHIPSEL pin is low
(internal address decode).
When clear, MEMCS16 is driven low whenever CHIPSEL goes low. (external address
decode). see Section 4.9.
For MEMCS16 pin to be enabled, the CS8900 must be in Memory Mode with the
MemoryE bit (Register 17, BusCTL, Bit A) set.
A
MemoryE
When set, the CS8900 may operate in Memory Mode. When clear, Memory Mode is
disabled. I/O Mode is always enabled.
B
DMABurst
When clear, the CS8900 performs continuous DMA until the receive frame is completely
transferred from the CS8900 to host memory. When set, each DMA access is limited to
28 µs, after which time the CS8900 gives up the bus for 1.3 µs before making a new
DMA request.
C IOCHRDYE When set, the CS8900 does not use the IOCHRDY output pin, and the pin is always
high-impedance. This allows external pull-up to force the output high. When clear, the
CS8900 drives IOCHRDY low to request additional time during I/O Read and Memory
Read cycles. IOCHRDY does not affect I/O Write, Memory Write, nor DMA Read.
D RxDMAsize This bit determines the size of the receive DMA buffer (located in host memory). When
set, the DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes.
F
EnableIRQ
When set, the CS8900 will generate an interrupt in response to an interrupt event
(Section 5.1). When cleared, the CS8900 will not generate any interrupts.
After reset, if no EEPROM is found by the CS8900, then the register has the following initial state. If an
EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 0111
64
DS150PP2
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