CS8900-CQ 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS8900-CQ Datasheet PDF : 132 Pages
| |||
CS8900
Register 15: Self Control (SelfCTL, Read/Write)
Address: PacketPage base + 0114h
F
HCB1
E
HCB0
D
HC1E
C
HC0E
B
A
9
8
7
HW HWSleepE SW
StandbyE
Suspend
SelfCTL controls the operation of the LED outputs and the low-power modes.
6
RESET
5-0
010101
BIT NAME
DESCRIPTION
5-0 010101
These bits provide an internal address used by the CS8900 to identify this as the Chip
Self Control Register. To write to this register, these bits must be 010101, where the
LSB corresponds to Bit 0.
6
RESET
When set, a chip-wide reset is initiated immediately. RESET is an Act-Once bit. This bit
is cleared as a result of the reset.
8
SWSuspend When set, the CS8900 enters the software initiated Suspend mode. Upon entering this
mode, there is a partial reset. All registers and circuits are reset except for the ISA I/O
Base Address Register and the SelfCTL Register. There is no transmit nor receive
activity in this mode. To come out of software Suspend, the host issues an I/O Write
within the CS8900’s assigned I/O space (see Section 3.7 for a complete description of
the CS8900’s low-power modes).
9
HWSleepE
When set, the SLEEP input pin is enabled. If SLEEP is high, the CS8900 is "awake", or
operative (unless in SWSuspend mode, as shown above). If SLEEP is low, the CS8900
enters either the Hardware Standby or Hardware Suspend mode. When clear, the
CS8900 ignores the SLEEP input pin (see Section 3.7 for a complete description of the
CS8900’s low-power modes).
A
HWStandbyE If HWSleepE is set and the SLEEP input pin is low, then when HWStandbyE is set, the
CS8900 enters the Hardware Standby mode. When clear, the CS8900 enters the
Hardware Suspend mode (see Section 3.7 for a complete description of the CS8900’s
low-power modes).
C HC0E
The LINKLED or HC0 output pin is selected with this control bit. When HC0E is clear,
the output pin is LINKLED. When HC0E is set, the output pin is HC0 and the HCB0 bit
(Bit E) controls the pin.
D HC1E
The BSTATUS or HC1 output pin is selected with this control bit. When HC1E is clear,
the output pin is BSTATUS and indicates receiver ISA Bus activity. When HC1E is set,
the output pin is HC1 and the HCB1 bit (Bit F) controls the pin.
E
HCB0
When HC0E (Bit C) is set, this bit controls the HC0 pin. If HCB0 is set, HC0 is low. If
HCB0 is clear, HC0 is high. HC0 may drive an LED or a logic gate. When HC0E (Bit C)
is clear, this control bit is ignored.
F
HCB1
When HC1E (Bit D) is set, this bit controls the HC1 pin. If HCB1 is set, HC1 is low. If
HCB1 is clear, HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D)
is clear, this control bit is ignored.
After reset, if no EEPROM is found by the CS8900, then the register has the following initial state. If an
EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 0101
62
DS150PP2
Share Link: 