CS8900 查看數據表（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register B: Buffer Configuration (BufCFG) continued

BIT NAME

DESCRIPTION

D MissOvfloiE If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from

1FFh to 200h. (A receive miss is said to have occurred if packets are lost due to slow

movement of receive data out of the receive buffers. When this happens, the RxMiss bit

(Register C, BufEvent, Bit A) is set, and the RxMISS counter (Register 10) is

incremented.)

F

RxDestiE

When set, there is an interrupt when a receive frame passes the Destination Address

filter criteria defined in the RxCTL register (Register 5). This bit provides an early

indication of an incoming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B).

After reset, if no EEPROM is found by the CS8900, then the register has the following initial state after reset. If

an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3.

0000 0000 0000 1011

56

DS150PP2

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