CS8900 查看數據表（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register 7: Transmit Configuration (TxCFG, Read/Write)

Address: PacketPage base + 0106h

F

E

D

C

B

A

9

8

7

6

5-0

16colliE

AnycolliE JabberiE Out-of- TxOKiE

windowiE

SQE

erroriE

Loss-of- 000111

CRSiE

Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear,

there is no interrupt.

BIT NAME

DESCRIPTION

5-0 000111

These bits provide an internal address used by the CS8900 to identify this as the

Transmit Configuration Register. To write to this register, these bits must be 000111,

where the LSB corresponds to Bit 0.

6

Loss-of-CRSiE If the CS8900 starts transmitting on the AUI and does not see the Carrier Sense signal

at the end of the preamble, an interrupt is generated if this bit is set. Carrier Sense

activity is reported by the CRS bit (Register 14, LineST, Bit E).

7

SQEerroriE When set, an interrupt is generated if there is an SQE error. (At the end of a

transmission on the AUI, the CS8900 expects to see a collision within 64 bit times. If

this does not happen, there is an SQE error.)

8

TxOKiE

When set, an interrupt is generated if a packet is completely transmitted.

9

Out-of-

windowiE

When set, an interrupt is generated if a late collision occurs (a late collision is a collision

which occurs after the first 512 bit times). When this occurs, the CS8900 forces a bad

CRC and terminates the transmission.

A

JabberiE

When set, an interrupt is generated if a transmission is longer than approximately

26 ms.

B

AnycolliE

When set, if one or more collisions occur during the transmission of a packet, an

interrupt occurs at the end of the transmission.

F

16colliE

If the CS8900 encounters 16 normal collisions while attempting to transmit a particular

packet, the CS8900 stops attempting to transmit that packet. When this bit is set, there

is an interrupt upon detecting the 16th collision.

After reset, if no EEPROM is found by the CS8900, then the register has the following initial state. If an

EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3.

0000 0000 0000 0111

NOTE:

Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and F

are interrupts for abnormal transmit operation.

52

DS150PP2

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