CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview

The CS8900 architecture is based on a unique,

highly-efficient method of accessing internal reg-

isters and buffer memory known as PacketPage.

PacketPage provides a unified way of controlling

the CS8900 in Memory or I/O space that mini-

mizes CPU overhead and simplifies software. It

provides a flexible set of performance features

and configuration options, allowing designers to

develop Ethernet circuits that meet their particu-

lar system requirements.

Integrated Memory

Central to the CS8900 architecture is a 4-Kbyte

page of integrated RAM known as PacketPage

memory. PacketPage memory is used for tempo-

rary storage of transmit and receive frames, and

for internal registers. Access to this memory is

done directly, through Memory space operations

(Section 4.9), or indirectly, though I/O space op-

erations (Section 4.10). In most cases, Memory

Mode will provide the best overall performance,

because ISA Memory operations require fewer

cycles than I/O operations. I/O Mode is the

CS8900’s default configuration and is used when

memory space is not available or when special

operations are required (e.g. waking the CS8900

from the Software Sleep state requires the host to

write to the CS8900’s assigned I/O space).

The user-accessible portion of PacketPage mem-

ory is organized into the following six sections:

PacketPage

Address

0000h - 0045h

0100h - 013Fh

0140h - 014Fh

0150h - 015Dh

0400h

0A00h

Contents

Bus Interface Registers

Status and Control Registers

Initiate Transmit Registers

Address Filter Registers

Receive Frame Location

Transmit Frame Location

36

Bus Interface Registers

The Bus Interface registers are used to configure

the CS8900’s ISA-bus interface and to map the

CS8900 into the host system’s I/O and Memory

space. Most of these registers are written only

during initialization, remaining unchanged while

the CS8900 is in normal operating mode. The

exceptions to this are the DMA registers which

are modified continually whenever the CS8900 is

using DMA. These registers are described in

more detail in Section 4.3.

Status and Control Registers

The Status and Control registers are the primary

means of controlling and getting status of the

CS8900. They are described in more detail in

Section 4.4.

Initiate Transmit Registers

The TxCMD/TxLength registers are used to initi-

ate Ethernet frame transmission. These registers

are described in more detail in Section 4.5. (See

Section 5.7 for a description of frame transmis-

sion.)

Address Filter Registers

The Filter registers store the Individual Address

filter and Logical Address filter used by the

Destination Address (DA) filter. These registers

are described in more detail in Section 4.6. For a

description of the DA filter, see Section 5.3.

Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage lo-

cations are used to transfer Ethernet frames to

and from the host. The host simply writes to and

reads from these locations and internal buffer

memory is dynamically allocated between trans-

mit and receive as needed. This provides more

efficient use of buffer memory and better overall

network performance. As a result of this dynamic

DS150PP2

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