CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Bus Interface Register:

DMA Start of Frame (Read only)

Address 0027h

Most-significant byte of offset value

Address: PacketPage base + 0026h

Address 0026h

Least-significant byte of offset value

The DMA Start of Frame Register contains a 16-bit value which defines the offset from the DMA base address

to the start of the most recently transferred received frame. See Section 5.4.

This register’s initial state after reset is: 0000 0000 0000 0000

Bus Interface Register:

DMA Frame Count (Read only)

Address 0029h

Most-significant byte of frame count

(most-significant nibble always 0h)

Address: PacketPage base + 0028h

Address 0028h

Least-significant byte of frame count

The lower 12 bits of the DMA Frame Count register define the number of valid frames transferred via DMA since

the last readout of this register. The upper 4 bits are reserved. See Section 5.4.

This register’s initial state after reset is: XXXX 0000 0000 0000

40

DS150PP2

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